The present invention generally relates to semiconductor devices, and in particular to a semiconductor device having a group III-V epitaxial semiconductor layer on a substrate.
The group III-V compound semiconductor materials are characterized by the high electron mobility due to the characteristic band structure pertinent to the material and are suitable for the active layer of fast-speed semiconductor devices. For example, GaAs and the mixed crystals thereof have been studied intensively for realizing such fast-speed devices. Particularly, InGaAs has the band structure that provides a performance superior to other devices constructed on the GaAs active layer in terms of the electron mobility and band structure that minimizes the transition of accelerated electrons from the .GAMMA.-valley corresponding to the ground state to other, excited states wherein the electron mobility is smaller. Further, InGaAs forms a two-dimensional electron gas when combined with other appropriate group III-V compound semiconductor layer with sufficient electron density. The latter feature is particularly advantageous for forming a device called HEMT (Miura et al., Jpn. J. Appl. Phys., 19, pp. L225-L227, 1980). Thus, this material is expected to play a major role in the future ultra-fast semiconductor devices.
On the other hand, there is a demand, in such a group III-V super-fast semiconductor devices, for a large diameter wafer to reduce the cost of the fabricated device. Thereby, a technique for producing such a large diameter wafer from the group III-V compound semiconductor material is needed. Conventionally, the production of such a large size wafer has been achieved either by growing a large diameter bulk crystal and slicing the wafer therefrom, or by growing a desired layer of group III-V compound semiconductor material on a commonly available large diameter silicon wafer. As the former approach encounters various difficulties such as difficulty in growing a large diameter bulk crystal of group III-V compound semiconductor material from the melt or difficulty in handling the heavy and brittle wafer, the latter approach of growing the group III-V compound semiconductor layer on the light and strong silicon wafer seems to be a more realistic solution. It should be noted that the production of large diameter silicon wafer is well established.
In taking up the latter approach, however, there arises a problem of discrepancy in the crystallographic as well as other physical properties between the group III-V compound semiconductor material and silicon. For example, the lattice constant of GaAs is about 4% larger than that of silicon while the thermal expansion coefficient of GaAs is larger by more than 200% than that of silicon. Thus, a simple epitaxial growth of GaAs or other group III-V compound semiconductor material on a silicon wafer is generally not successful.
This problem of heteroepitaxial growth of the group III-V compound semiconductor material on silicon has been solved by interposing a layer of amorphous GaAs between the silicon wafer and the group III-V compound semiconductor layer to be grown on the wafer (Akiyama M. et al., J. Cryst. Growth, vol. 68, no. 21, 1984).
On the other hand, the group III-V compound semiconductor layer thus obtained generally involves substantial amount of dislocations and other defects that are formed in the amorphous GaAs buffer layer. It should be noted that these dislocations are created at the boundary between the wafer and the buffer layer at the time when the amorphous layer is crystallized (Akiyama et. al., op cit). Once created, the dislocations propagate into the group III-V compound semiconductor layer, passing through the buffer layer that includes a nucleation layer. Because of this, the dislocation density in the group III-V compound semiconductor layer is intolerably high, in the order of 10.sup.8 cm.sup.-2 or more. Such a material is useless for the active layer of the high speed semiconductor devices.
In addition to the problem of dislocations, the semiconductor devices formed on the foregoing heteroepitaxial structure has a problem of excessive leakage current flowing from the active layer to the substrate. When such leakage current flows, the electric isolation of devices on the substrate is naturally deteriorated. When the leakage current is large enough to cause poor device isolation, the substrate can no longer used for the substrate of integrated circuits. Further, there occurs an interference between adjacent devices known as the "side gate effect." For example, the threshold voltage of a device such as MESFET may change by the gate voltage applied to an adjacent device.
In order to avoid such undesirable interference, the conventional III-V semiconductor layers on the substrate employ undoped GaAs for the buffer layer to secure a high resistivity. Alternatively, there has been practiced to provide a reversely biased p-n junction between the active layer and the substrate. However, such a measure cannot reduce the leakage current below about 10.sup.-3 amperes, which is not satisfactory for the substrate to be used for the compound semiconductor integrated circuits.